Date of Award

2011

Document Type

Master Thesis

Degree Name

Master of Engineering (Research)

Department

Electronic Engineering

First Advisor

Dr. Richard Guinee

Abstract

The work that is presented in this thesis documents the results obtained from the pseudo random binary sequence (PRBS) cable testing method which utilises a pseudo noise (pN) sequence as a test stimulus to localise faults on a transmission line. The work targets the proof of concept of the PRBS method in a Coaxial cable as well as its eventual evaluation for fault testing accuracy and performance on a real-world underground steel wired armour (SWA) cable. Further, a novel hardware implementation of the method utilising a Field Programmable Gate Array (FPGA) is presented. The theory of the PRBS test method relies on the fact that any cable forms a transmission line medium which will reflect some of the signal power at points where the transmission line parameters change. Such discontinuities occur typically at junction terminals or at points where a fault is present. The auto correlation (ACR) property of the PRBS test stimulus is used to visualise reflections and their characteristics generated on the transmission line under test through cross correlation of the original sequence with the response captured from the medium under test. The evaluation of the method at the Tyndall National Institute utilises standard of- the-shelf test equipment in combination with a customised correlation software. The tests have been conducted at the under the National Access Program (NAP144) and it was found that it was well possible to localise faults on the tested cables. The results obtained from a 5011 coaxial cable demonstrated clearly the type of the fault introduced on to the cable, whereas the results obtained from the 4-core SWA cable introduced a number problems related to the conductor geometrical arrangement in the cable. Never the less it was found that useful and accurate results could be obtained from the cable. An integration of the test setup into a standalone test solution led to the development of a correlation algorithm utilising a Field Programmable Gate Array (FPGA), a high speed Analogue to Digital Converter (ADC) and a high speed Digital to Analogue Converter (DAC). The correlation processes in this setup is described using the Hardware Descriptive Language (HDL) Verilog. The design described in this work is parameter scalable which provides a trade off between correlation speed and resource utilisation. The design is validated through comparison between the results previously obtained at the Tyndall National Institute and results obtained from the designed hardware. It was found that the correlator design is well capable of reproducing the results previously obtained and is thus considered fit for its purpose. A detailed description of the correlator design is given including a discussion on the design choices.

Access Level

info:eu-repo/semantics/openAccess

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