Date of Award
2004
Document Type
Master Thesis
Degree Name
Master of Engineering (Research)
Department
Electronic Engineering
First Advisor
Dr. John Horan
Abstract
The clock generator is a critical component in high-speed wireline communication systems. The clocks in these systems mark time at precise regular intervals. Any deviation of the clock edges from these ideal time points is called jitter and it degrades the overall integrity of the communication system. This thesis looks at both phase locked loops (PLLs) and delay locked loops (DLLs) and their ability to provide these precise clocks. Expressions for the thermal noise-induced jitter in both the PLL and DLL are compared. From this, the DLL is shown to possess the potential for better jitter performance. However, to realise the potential of the DLL, another source of jitter peculiar to the DLL has to be reduced. This jitter in DLLs is caused by Static Phase Offset (SPO). The thesis details the causes of SPO and describes a number of good design practices for reducing it. It then describes an input and feedback clock phase interpolation technique which reduces SPO by half. Finally a novel chopping technique is used to essentially eliminate SPO resulting in a DLL which is ideal for high-speed wireline communication systems.
Some of this work was published at the lEE Irish Signals and Systems Conference, which took place at Queens University Belfast, in June 2004.
Recommended Citation
Kennedy, Ian, "Development of a Low Jitter Multiplying Delay Locked Loop" (2004). Theses [online].
Available at: https://sword.cit.ie/allthe/599
Access Level
info:eu-repo/semantics/openAccess