Date of Award


Document Type

Doctoral Thesis

Degree Name

Doctor of Philosophy


Electronic Engineering

First Advisor

Dr. John Horan


This thesis presents a methodology for the development of high performance video clock synthesisers that have high (2000) input to output clock multiplication ratios. The synthesisers are required to be compatible with standard CMOS technologies and they must exhibit very low drift between their input and output clocks.

The methodology used borrows techniques established for RF synthesisers in the GHz range. In the RF domain there are significant constraints on spectral spread and because of this there has been significant interest in phase noise generated by intrinsic device noise. Simple and accurate models were developed that help understand the up and down conversion of this device noise into phase noise. Using these ideas all possible sources of noise in the video synthesiser were studied and optimised. A key result of this analysis was a redesign of the bias circuitry leading in itself to a performance improvement of a factor of eight over a conventional bias scheme.

In RF applications there is usually a small multiplication ratio between input and output clocks. The bandwidths of the synthesiser loops are beyond the 1/f noise corner of the oscillators making the 1/f noise in the oscillator less important. The challenge with video clock synthesisers is that there is a large multiplication ratio and a low bandwidth requirement so this makes the 1/f noise in the synthesiser important. The 1/f noise causes a significant drift between input and output clocks. This drift is particularly relevant for video clocks that determine the sampling instants of the analogue video signal. The drift in these clocks leads to erroneous or missing video samples which causes bad or lost pixels in a displayed image.

The clock synthesiser described in this thesis performed frequency multiplication of an input clock ranging from 15kHz to 5MHz with a programmable multiplication ratio of 4 to 1024. The circuit was implemented on a chip using a commercial 0.25pm CMOS process. A sample of measured drift in the optimised device is 0.42ns for a 48kHz reference and a multiplication ratio of 584. These measured drift results represent the lowest reported to date.

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