Date of Award


Document Type

Master Thesis

Degree Name

Master of Engineering (Research)


Institute of Technology Tralee

First Advisor

Dr. James Prendergast


The purpose of this study is to investigate and validate the mechanism of hot carrier degradation of the LDMOS device. The LDMOS device is a new technology to Analog Devices, and a relatively new topic to the semiconductor industry, evident from the limited published research in the field. A prerequisite for device release on a product in the market place, is comprehensive hot carrier reliability testing, as hot carrier degradation has evolved as one of the foremost concerns in submicron devices. Both the high voltage and the structural difference of the LDMOS device, from standard MOSFET device, pose a hot carrier investigation challenge. Establishing the hot carrier mechanism involves gaining an understanding of the internal electric fields, the current paths and the basic mechanics of the device. An accelerating factor i.e. increased voltage or current or temperature is required and must be seen to exist at both use and stress condition, and without causing any new failure mechanisms to be introduced. Interpretation of the resultant stress test device parametric degradation typically yields a device lifetime at the stress conditions, and analysis and models are used to predict lifetime at the use conditions. This is the approach of the investigative research undertaken in this thesis. The outcome will present a hot carrier mechanism, an interpretation of observed device degradation, and methods of device lifetime presentation, for the LDMOS device. An on-line wafer level test providing early feedback on maverick fabrication lots will also be proposed. While it is expected that the objectives will be achieved, continued study into aspects of the results are a natural outcome of most investigations. 11

Access Level