Date of Award


Document Type

Master Thesis

Degree Name

Master of Engineering (Research)


Electronic Engineering

First Advisor

Dr. John Horan


High speed, medium resolution ADC’s, are required for many applications, including wireless receivers, ultrasound systems, wireline interfaces, cameras and camcorders. Low power dissipation is important, particularly for portable equipment where battery life must be maximised. The pipeline ADC architecture is particularly suited to such applications. Its strength comes from the manner in which it performs a conversion, distributing the work in time and amongst successive stages. These stages operate concurrently, maintaining high throughput. Each stage is made up of a fully differential switched capacitor sample-and- hold amplifier and some other circuitry. Designing these circuits to operate at l00MHz is extremely challenging.

This work describes the design of a low power 10-bit, l00MSample/s pipeline ADC for a standard, dual gate oxide, digital 0.18pm CMOS process. The integration of such a converter into standard CMOS allows subsequent signal processing to be carried out in the digital domain. This is highly desirable because finer geometry processes improve all aspects of digital circuit performance. The same is not true of analog circuitry however, where transistor scaling degrades performance and makes design increasingly challenging.

All the mechanisms that cause deviation from ideal behaviour are studied in this work to allow accurate prediction of the ADC’s performance. These include bond-wire inductance, parasitic capacitances, thermal noise and clock jitter. Even with these effects taken into consideration this ADC still demonstrates excellent performance. It maintains better than 9.25 effective number of bits over the full Nyquist band with a nominal core power dissipation of II4mW.

This work was supported in full by Ceva Inc., Enterprise Ireland and Cork Institute of Technology.

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